In general, read-only-memories (hereinafter referred to as ROMs) are used for storing data information in a permanent, non-volatile form. Semiconductor ROMs find particular application in digital electronic equipment such as computers, office equipment, and game machines where they are used to store permanent data information. Such permanent data information includes control microprograms, electronic games, printer fonts, etc. With the continuing advances in digital electronics and the corresponding need for larger quantities of data information, the demand for cheaper and higher capacity ROMs is growing.
Semiconductor ROMs generally store their data information in arrays of memory cells, wherein each memory cell is a single transistor. The data bits held by the memory cell transistors are permanently stored in the physical or electrical properties of the individual memory cell transistors. For example, in a typical ROM wherein the memory cell transistors are MOSFETs (metal-oxide-semiconductor field effect transistors), memory cell transistors having a first threshold voltage store data bits of value "0" whereas memory cell transistors having a second threshold voltage different from the first threshold voltage store data bits of value "1".
Semiconductor ROMs are generally formed by intersecting a plurality of bitlines which have been diffused into a semiconductor substrate with a plurality of wordlines lying over the substrate. The wordlines are physically separated from the bitlines and the substrate by a thin gate oxide layer such that an array of memory cell MOSFET transistors is formed. In the array, the wordlines serve as gates for the memory cell transistors while the bitlines serve as source and drain diffusion regions. Then, by properly adjusting the dopant concentrations of the channel regions of the individual memory cell transistors, the memory cell transistors are programmed to exhibit the threshold voltages corresponding to the data bits they store.
In the case of mask-programmable read-only-memories (or, alternatively, mask ROMs or simply MROMs), the coding of the data bits onto the memory cell transistors is generally performed by implanting ions into the channel regions of the appropriate memory cell transistors, thereby adjusting their threshold voltages. This step of coding the data into the ROM array structure through ion implantation is performed using a code mask which permits the implantation of ions into only certain regions (the desired memory cell transistor channel regions) of the semiconductor. The use of a code mask leads to the name mask ROM. Mask ROMs are particularly useful because they can be partially manufactured and stored without being programmed. Some time later, they can be programmed using an ion implantation mask that is custom-made for a particular application. After the programming step, only a few post-processing steps are needed before delivering the custom-programmed MROMs to a customer.
FIG. 1 is a simplified, two-dimensional overhead layout schematic view of a portion of a typical MROM array structure according to the prior art. This MROM array structure includes a substantially rectangular sub-region 2 with vertices W, X, Y, and Z. A three-dimensional cut-out view of sub-region 2 is shown in FIG. 2 to more clearly illustrate this prior art MROM array structure.
The prior art MROM array structure of FIG. 1 and FIG. 2 implements a NOR-type ROM (as will be described below). It is called a flat cell and is described in "Symposium on VLSI Circuits", 1988, pp. 85-86. The prior art MROM array structure comprises a semiconductor substrate 4 of a first conductivity type which is typically, but not necessarily, p-type. The structure also comprises a plurality of substantially parallel, elongated, conductive regions 6 formed on the top surface of substrate 4. These conductive regions 6 are called bitlines and are diffusion regions of a second conductivity type, typically n-type. The prior art MROM array structure further comprises metal-to-diffusion contacts 8 which electrically connect bitlines 6 to metal bitlines 10. For simplicity and in order to better illustrate the prior art MROM array structure, metal bitlines 10 are not shown in FIG. 1 or FIG. 2.
The prior art MROM array structure of FIG. 1 and FIG. 2 further comprises a plurality of substantially parallel, elongated, conductive polysilicon strips 12. These polysilicon strips 12 are called wordlines, and they cross over bitlines 6 at substantially right angles. Each of the bitlines 6 are physically and electrically isolated from each of the wordlines 12 by a gate dielectric 14. Additionally, wordlines 12 are physically and electrically separated from each other by a field dielectric 16, and an insulation layer 18 physically and electrically isolates metal bitlines 10 from wordlines 12. For simplicity, gate dielectric 14, field dielectric 16, and insulation layer 18 are not shown in FIG. 1. Additionally, gate dielectric 14, field dielectric 16, and insulation layer 18 are typically of silicon dioxide, SiO.sub.2, hereinafter referred to as oxide.
In the prior art MROM array structure of FIG. 1 and FIG. 2, the substrate surface regions directly underneath a wordline and between any two bitlines form channel regions of memory cell MOSFET transistors. In FIG. 1, one such memory cell transistor 20 has a channel region indicated by the rectangle with vertices B, C, D, and I. The channel region of memory cell transistor 20 is formed on the surface of substrate 4 between bitline 6b and bitline 6c, directly below wordline 12c. In this way, an array of MOSFET memory cell transistors is formed with wordlines 12 serving as gate electrodes and bitlines 6 serving as source and drain diffusion regions. In the prior art MROM array structure of FIG. 1 and FIG. 2, the area regarded as a single memory cell unit area is indicated by the rectangular region with vertices A, C, E, and G. However, the actual memory cell transistor that stores the data bit information occupies only the rectangular area with vertices B, C, D, and I.
The prior art MROM array of memory cell transistors is typically placed within a ROM chip along with memory cell access circuitry for accessing the memory cell transistors in the array. The memory cell access circuitry typically includes row (wordline) address decoder and driver circuits, column (bitline) address decoder and driver circuits, bitline sense amplifier circuits, and output buffer circuits. These memory cell access circuits are all well known in the art, and, therefore, will not be described or illustrated herein. Additionally, although only one metal-to-diffusion contact 8 is shown for each bitline 6, metal-to-diffusion contacts 8 are periodically placed along bitlines 6 in order to provide low-resistance electrical connections from metal bitlines 10 to bitlines 6 to the channels of the memory cell transistors. The placement of the metal-to-diffusion contacts 8 is well known by those skilled in the art.
As mentioned above, the prior art MROM array structure of FIG. 1 and FIG. 2 implements a NOR-type ROM. To describe the electrical operation of such a ROM, reference will be made to FIG. 3 which shows an equivalent circuit diagram of sub-region 2 of the prior art MROM array structure of FIG. 1 and FIG. 2.
Assume that one desires to read out the data bit stored by memory cell transistor 20. To do so, the memory cell access circuitry applies a power source voltage, Vcc, of typically 5 volts to bitline 6b, grounds (applies substantially zero volts to) bitline 6c, and leaves all other bitlines 6 floating (disconnected). Simultaneously, the memory access circuitry applies a read voltage of about 2 volts to wordline 12c while grounding all other wordlines 12. In this way, memory cell transistor 20 is selected (i.e. it is given a gate-to-source voltage of +2 V and an initial drain-to-source voltage of +5 V). If memory cell transistor 20 has not been programmed such that it has a threshold voltage less than 2 volts, the applied voltages will bias it into the active region of operation causing it to turn on and conduct current from bitline 6b to bitline 6c. Sense amplifier circuits electrically connected to bitline 6b through metal-to-diffusion contact 8b and metal bitline 10b will sense the current flow (and the corresponding drop in voltage of bitline 6b) and will drive the output buffer circuits to read out a logic state "1". Similarly, if memory cell transistor 20 has been programmed such that it has a threshold voltage greater than 2 volts, the applied gate-to-source voltage will not be sufficient to bias it into the active region. In this case, memory cell transistor 20 will not turn on or conduct significant current, thus causing the sense amplifier circuits to drive the output buffer circuits to read out a logic state "0". Note that it is equally possible to have the higher threshold voltage represent a logic state "1" and the lower threshold voltage represent a logic state "0".
FIG. 4 is a cross-sectional view of sub-region 2 of FIG. 1 taken along the line a-a'. Likewise, FIG. 5 is a cross-sectional view of sub-region 2 of FIG. 1 taken along the line b-b'. These two figures will be used to illustrate the following brief description of the manufacturing process of the prior art MROM array structure.
Referring to FIG. 4, on the surface of a semiconductor substrate 4 of a first conductivity type, predetermined active diffusion regions 6 of a second conductivity type are formed to serve as bitlines 6. Over the surface of substrate 4, a gate oxide layer 14, conductive polysilicon wordlines 12, and an insulating oxide layer 18 are successively formed. Finally metal bitlines 10 are deposited over insulating oxide layer 18. Metal bitlines 10 are deposited such that they substantially overlie bitlines 6 when viewed from above.
Referring to FIG. 5, on the surface of a semiconductor substrate 4 of a first conductivity type, a gate oxide layer 14 is formed. Conductive polysilicon is then grown in predetermined regions above gate oxide 14 in order to form wordlines 12. Strips of field oxide 16 and a layer of insulating oxide 18 are then grown between and over wordlines 12, respectively, in order to insulate the individual wordlines from each other and from a metal layer 10.
In order to increase the storage capacity of a conventional, prior art MROM array, it is desirable to reduce the size of the individual memory cells. However, two aspects of the manufacturing process of the prior art MROM array structure limit the degree to which the array structure dimensions can be reduced. The first limitation is the minimum feature size of the particular photolithographic process that is used to fabricate the MROM. The minimum feature size of the photolithographic process may limit one or more of the dimensions in the MROM array structure. For example, the photolithographic minimum feature size may limit the minimum proximity of wordlines 12 to one another, the minimum proximity of metal bitlines 10 to one another, the minimum proximity of bitlines 6 to one other (and thus the length of the memory cell transistor channel regions), the minimum widths of wordlines 12, the minimum widths of metal bitlines 10, or the minimum widths of bitlines 6. Of these, generally the most important is the minimum spacing between adjacent wordlines--the minimum width of field dielectric strips 16. Without advances in the photolithographic process which effectively reduce the minimum feature size, a reduction in the size of the memory cells in the prior art MROM array structure is not possible.
But even if the photolithographic process is improved to allow the minimum feature size to be reduced, there is another practical limitation that prevents the production of prior art MROM array structures of higher density. This practical limitation is a result of the code mask ion implantation step that is performed to program the memory cell transistors. During this step, care must be taken so that dopant ions are implanted only into the channel regions of the appropriate memory cell transistors whose threshold voltages need to be altered in order to hold the correct data information. This requires very precise alignment of the code mask so that adjacent memory cell transistors will not be programmed incorrectly. Since perfect alignment is not possible, some spatial margin between adjacent memory cell transistors must be guaranteed during the code implantation process, thereby limiting the minimum proximity of adjacent memory cells to one another. Additionally, some spatial margin between adjacent memory cell transistors must be allocated for the out-diffusion of ions during the thermal processing steps such as annealing that follow the code ion implantation. This is especially true for boron p-type implantation (to raise the threshold voltage) since boron has a very high constant of diffusivity.
These aspects of the manufacturing process, therefore, limit the minimum dimensions for reliably producing the prior art MROM array structure. This in turn limits the data bit storage density of the MROM. Since the cost of semiconductor devices is directly related to the physical semiconductor area that is used, these process limitations hamper attempts to lower the cost of prior art MROMs through a reduction in the dimensions of the MROM array structure. Additionally, it is difficult to produce higher density MROMs by simply increasing the size of the MROM die because production yield is inversely related to semiconductor area. Thus, these process limitations also hamper attempts to reliably and profitably produce further integrated MROMs with greater storage capacity.
In U.S. Pat. No. 5,200,355, Choi et. al. propose a NOR-type MROM array structure for reducing the proximity of wordlines to one another, thereby decreasing the size of the MROM memory cell area and increasing the integration of the MROM array. The inventors propose a manufacturing method for producing a NOR-type MROM array with wordlines separated by a distance of only by 1000-3000 angstroms, as determined by a nitride layer. Although the method for an MROM array structure disclosed by Choi et. al. does increase the integration of the MROM array, even further integration of the MROM array into a smaller physical semiconductor area is desired. However, any method for further integration of the MROM array must not subject the array to an increased likelihood of incorrect coding of the data bits into the memory cells during the code mask ion implantation step or during post-processing steps.